Metal oxide semiconductor field-effect transistor (MOSFET) devices in very-large-scale integrated (VLSI) devices exhibit performance degradation when under continued influence of negative or positive bias temperature instability (NBTI/PBTI). NBTI occurs when a gate-to-source (GSS) voltage of a p-channel MOSFET device is kept at a negative supply voltage level at elevated temperatures for a prolonged period of time, often referred to as stress phase. On the other hand, PBTI occurs when n-channel MOSFET devices are positively biased at elevated temperatures for a prolonged period of time. NBTI may also occur in n-channel MOSFET devices when being negatively biased in the accumulation regime. Although both effects can be recovered to a certain degree, over the lifetime of a MOSFET device the NBTI effect prove to be more detrimental since vital MOSFET parameters such as the threshold voltage or the transconductance. The degradation of the parameters usually exhibits a logarithmic dependency on time.
Several approaches have been taken in the prior art to combat NBTI/PBTI related degradation of FET device parameters in order to improve the functionality of integrated circuitry employing such devices.
Ricketts, A. et al.: “Investigating the impact of NBTI on different power saving cache strategies”, Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2010, pages 592-597, disclose power saving strategies for SRAM cells with respect to NBTI induced parameter degradation.
Li, L. et al.: “Proactive NBTI mitigation for busy functional units in out-of-order microprocessors”, Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2010, pages 411-416, disclose proactive NBTI recovery schemes for functional units in microprocessors.
Shin, J. et al.: “A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime”, ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture, pages 353-362, disclose proactive NBTI recovery scheduling of FET devices of microarchitecturally redundant functional units.
The document U.S. Pat. No. 8,063,655 B2 discloses a method for reducing NBTI degradation of MOSFET devices, including forward biasing the MOSFET device when a shift in threshold voltage exceeds a predetermined value.
The document US 2012/0159276 A1 discloses an automated guardband compensation system for compensating for degradation in the guardband of clocked data processing circuits within a data processing system.
Yang, J. B. et al.: “A novel empirical model for NBTI recovery with the modulated measurement time frame”, Proceedings of the 13th IPFA 2006, Singapore, page 33, describes the empirical model of the NBTI recovery with respect to the influence of the measurement associated with the removal of stress in comparison to the long-term ageing stress.
Kumar, S. V. et al.: “NBTI-Aware Synthesis of Digital Circuits”, Proceedings of the IEEE/ACM Design Automation Conference, June 2007, disclose calculating cell delay based on the switching probability and adjusting duty cycles of switching circuits with respect to a NBTI model.
There is a need for solutions that allow MOSFET devices to recover from any temporary NBTI/PBTI induced degradation of device parameters upon entering an operational state when exiting a NBTI/PBTI stress phase.